Complex-valued multiplier-and-accumulator

ABSTRACT

When we use multi-mode Multiplier-And-Accumulator with the double-precision Complex-Valued Multiplier-And-Accumulator as our main configuration, the different precisions and digital modes make it more flexible, compared to the traditional real number Multiplier-And-Accumulator. In addition, it does not have the data alignment problem that happen in the traditional application of different precision Subword Parallel processors. This kind of Multiplier-And-Accumulator takes a double-precision Complex-Valued Multiplier-And-Accumulator as the main configuration, with four double-precision real-valued multipliers and several groups of accumulators to assist in different modes of operation. Each double-precision real-valued multiplier can be segmented into four single-precision multipliers, and then we get double-precision multiplier products by means of displacement addition. If we take two real numbers that are continuous in time sequence as the real number input and imaginary number input for the original complex-valued multipliers, for example, the accumulated products figured out include not only the present output accumulated product summation but also include the output accumulated product summation of the previous time and the next time. So, as long as we move the next output accumulated product summation to the correspondingly previous accumulator, real-valued double-precision accumulative addition is ready for running. The product from the four single-precision multipliers in each double-precision real-valued multiplier can be combined to each other and accumulated to a complex-valued accumulator, thus they form four parallel operating single-precision accumulators; if we take continuous four groups of single-precision as input, through proper multiplexing and accumulated value moving, we can realize averagely sixteen single precision real-valued multiplication-additions within one instruction.

FIELD OF THE INVENTION

[0001] This Multiplier-And-Accumulator can perform double- (single-) precision complex (real) number operations, suitable for multiplication-addition for all types of digital signals including finite impulse response filter, infinite impulse response filter, match filter, correlation coefficient operation, convolutional operation, transformation between time and frequency signal etc., or for digital communication systems, digital equalizer and complex number filter as examples.

BACKGROUND OF THE INVENTION

[0002] Multiplier-And-Accumulator is the core processing unit in digital signal processors. In the application of programmable digital signal processors, such as in video, audio, voice, and telecommunication, we often use finite impulse response filter, infinite impulse response filter, match filter, correlation coefficient operation, convolutional operation, transformation between time field and frequency field, etc. So it becomes a significant part of digital signal processors in order to perform the high-dimensional vector product accumulation in high speed.

[0003] There are three methods to accelerate Multiply-And-Accumulate. The first is to optimize Multiply-And-Accumulate arithmetic; this method reduces the delay time and to speedup with different Booth Multiplier architecture. The second way is the auxiliary function of digital signal processors. In the program sequence control unit, multiplication-and-accumulation are often executed with a looping counter, in order to avoid overhead looping operations needed for detecting data ending conditions, so that the digital signal processor can perform the multiplication-addition in full speed. Besides, because the two vectors to be multiplied and accumulated are often different from each other in length, such as finite impulse response filter, match filter, and so on, coefficient vector will be read in a cyclic way, thus, digital signal processors usually provide cyclic addressing to accelerate the accessing of the cyclic data. Both of the above ways are traditional ones for accelerating multiplication-addition, maximizing the Multiplier-And-Accumulator efficiency through depressing the extra operations on the hardware or software.

[0004] The third method is to execute the MAC operations in the parallel Multiplier-And-Accumulator configuration. The MAC operations are accelerated by means of parallel-operating Multiplier-And-Accumulators, using Single Instruction Multiple Data (SIMD) as its processor architecture. However, it has higher hardware cost, and in the operations of different precision, the time required for the operation is the same, so the hardware is optimally efficient. Therefore, the so-called subword parallel digital signal processor is derived. Because different applications require different signal precision, a high-precision operation can be segmented into several low-precision operations, thus parallel operations can be performed. Usually, most of these kinds of design are for simple addition, subtraction, and logic operations. In recent years, the subword parallel configuration has been adapted in the Multiplier-And-Accumulator to accelerate multiply-and-accumulation. This design can speedup operation speed, however, the data accuracy is lowered down. Several low-precision data are read in one time, so, additional hardware or software are required for the data alignment. Options to solve this problem are to add groups of alternate buffer storage, or to add a fault bit indicator for alignment and then to load it up into the buffer storage to operate. In this case, each group of input needs extra data alignment processing.

[0005] In summary, Multiplier-And-Accumulator configurations with Subword Parallel operation can effectively step up data signal processing efficiency in multiplication-addition, but the data alignment requires extra processing for the different precision data.

SUMMARY OF THE INVENTION

[0006] The present invention demonstrates a wholly improved Multiplier-And-Accumulator configuration makes it more flexible to perform multiplication-addition, especially for the complex number multiplication-and-accumulation in the communicational signal processing.

[0007] Also, another advantage of the present invention is Subword Parallel operation. So, when a single-precision value operation is in process, support can be drawn from parallel ways, using double-precision hardware, to get accelerated multiplication-accumulation.

[0008] Furthermore, Complex-Valued Multiplier-And-Accumulator can solve the data alignment problem occurring in general Subword Parallel arithmetic units, thus extra hardware and software operation are omitted.

[0009] While the invention is susceptible to various modifications and alternative forms, certain illustrative embodiments thereof have been shown by way of example in the drawing and will herein be described in detail.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The invention will now be described by way of example with reference to the accompanying Tables and Figures in which:

[0011] FIGS. 1(a)-(b) N×N double-precision complex- (real-) valued Multiplier-And-Accumulator Configuration and N×N double-precision multiplier segmented

[0012]FIG. 1(a) N×N double-precision complex- (real-) valued Multiplier-And-Accumulator Configuration

[0013]FIG. 1(b) N×N double-precision multiplier segmented as secondary number group into four single-precision multipliers

[0014]FIG. 2 N×N double-precision real number multiplier for K-tap finite impulse response filter operation program

[0015]FIG. 3 N×N segmentation of double-precision multiplier into single-precision

[0016]FIG. 4 $\frac{N}{2} \times \frac{N}{2}$

[0017] single-precision Complex-Valued Multiplier-And-Accumulator configuration

[0018]FIG. 5 $\frac{N}{2} \times \frac{N}{2}$

[0019] single-precision real-valued Multiplier-And-Accumulator for K-tap finite impulse response filter operation program

[0020]FIG. 6 $\frac{N}{2} \times \frac{N}{2}$

[0021] single-precision real-valued Multiplier-And-Accumulator configuration

[0022]FIG. 7 summary of different-mode efficiency in Complex-Valued Multiplier-And-Accumulator

REFERENCE NUMBER OF THE ATTACHED DRAWINGS:

[0023]1 . . . AR real number buffer storage 1

[0024]2 . . . AI.Imaginary number buffer storage 1

[0025]3 . . . real number buffer storage 2

[0026]4 . . . Imaginary number buffer storage 2

[0027]101 . . . P0 product 1

[0028]102 . . . P1 product 2

[0029]103 . . . P2 product 3

[0030]104 . . . P3 product 4

[0031]201 . . . ACCR real number accumulation buffer storage

[0032]202 . . . ACC-AUX auxiliary accumulation buffer storage

[0033]203 . . . ACCI Imaginary number accumulation buffer storage

[0034]301 . . . Y(n) output

[0035]302 . . . Y(n−1) output

[0036]401 . . . M1 Accunulator

[0037]402 . . . M2 Accumulator

[0038]403 . . . M3 Accumulator

[0039]404 . . . MUXI multiplexer

[0040]500 . . . C0 double-precision multiplier

[0041]501 . . . C1 double-precision multiplier

[0042]502 . . . C2 double-multiple precision multiplier

[0043]503 . . . C3 double-precision multiplier

[0044]504 . . . C4 double-precision multiplier

[0045]510 . . . AX double-precision multiplier

[0046]511 . . . BX double-precision multiplier

[0047]512 . . . AXH double-precision multiplier high position

[0048]513 . . . AXL double-precision multiplier low position

[0049]514 . . . BXH double-precision multiplier high position

[0050]515 . . . BXL double-precision multiplier low position

[0051]520 . . . SM0 single-precision multiplier

[0052]521 . . . SM1 single-precision multiplier

[0053]522 . . . SM2 single-precision multiplier

[0054]523 . . . SM3 single-precision multiplier

[0055]524 . . . pp0 partial product

[0056]525 . . . pp1 partial product

[0057]526 . . . pp2 partial product

[0058]527 . . . pp3 partial product

[0059]530 . . . SH0 left-shift $\frac{N}{2}$

[0060] bit unit

[0061]531 . . . SH1 left-shift $\frac{N}{2}$

[0062] bit unit

[0063]532 . . . left-shift-N-bit unit

[0064]533 . . . Wallet Tree Adder

[0065]534 . . . AX×BX double-precision product

[0066]601 . . . CR(k) filter coefficient real number part 1

[0067]602 . . . CI(k) filter coefficient imaginary number part 1

[0068]603 . . . CR(k+1) filter coefficient real number part 2

[0069]604 . . . CI(k+1) filter coefficient imaginary number part 2

[0070]605 . . . XR(n−k) input real number part 1

[0071]606 . . . XI(n−k) input Imaginary number part 1

[0072]607 . . . XR(n−k−1) input real number part 2

[0073]608 . . . XI(n−k−1) input imaginary numbers part 2

[0074]701˜716 . . . A0˜A15 single-precision multiplier

[0075]801˜808 . . . B0˜B7 accumulator

[0076]901˜904 . . . acc0˜acc3 complex-valued accumulating register

[0077]1001 . . . Y(n) output

[0078]1002 . . . Y(n−1) output

[0079]1101˜1104 . . . S0˜S3 output adder

[0080]1101˜1104 . . . S0˜S4 output adder

[0081]1201 . . . real-number data movement

[0082]1202 . . . imaginary-number data movement

[0083]1301 . . . C(k) filter coefficient 1

[0084]1302 . . . C(k+1) filter coefficient 2

[0085]1303 . . . C(k+2) filter coefficient 3

[0086]1304 . . . C(k+3) filter coefficient 4

[0087]1305 . . . X(n−k) input 1

[0088]1306 . . . X(n−k−1) input 2

[0089]1307 . . . X(n−k−2) input 3

[0090]1308 . . . X(n−k−3) input 4

[0091]1401˜1413 . . . acc0˜acc12 accumulating register

[0092]1501 . . . Y(n) output 1

[0093]1502 . . . Y(n−1) output 2

[0094]1503 . . . Y(n−2) output 3

[0095]1504 . . . Y(n−3) output 4

[0096]1601˜1603 . . . register data moving

[0097]1701 . . . AXH multiplicand most significant bits

[0098]1702 . . . AXL multiplicand least significant bits

[0099]1703 . . . BXH multiplier most significant bits

[0100]1704 . . . BXL multiplier least significant bits

[0101]1801 . . . partial product 1

[0102]1802 . . . partial product 2

[0103]1803 . . . partial product 3

[0104]1804 . . . partial product 4

[0105]1901 . . . multiplication

[0106]1902 . . . addition

[0107]2001 . . . Multiplier-And-Accumulator input value

[0108]2002 . . . product

[0109]2003 . . . AR BR AI BI corresponding register value

[0110]2004 . . . p0˜p3 product

[0111]2101 . . . accumulated product of present iteration

[0112]2102 . . . accumulated product of previous iteration

[0113]2103 . . . accumulated product of next iteration

[0114]2201 . . . t=n−4 previous fourth time

[0115]2202 . . . t=n present time

[0116]2301 . . . present output accumulated product

[0117]2302 . . . previous output accumulated product

[0118]2303 . . . previous two output accumulated product

[0119]2304 . . . previous three output accumulated product

DETAILED DESCRIPTION OF THE INVENTION

[0120] The present invention demonstrates a new configuration, suitable for different data formats, including multiplication-and-accumulations of complex/real-valued and single-/double-precision data. In addition, the data alignment processing in the general single-precision operation can be avoided. My configuration has several combinations in different mode.

[0121] To achieve the above goal, the invention take double-precision complex-valued multiplier-And-Accumulator as the main configuration. FIG. 1(a) shows four double-precision Multiplier-And-Accumulators, such as C0 double-precision multiplier (500), C1 double-precision multiplier (501), C2 double-precision multiplier (502) and C3 double-precision multiplier (503) respectively; and three accumulators as M1 Accumulator (401), M2 Accumulator (402) and M3 Accumulator (403).

[0122] Each of the four double-precision Multiplier-And-Accumulators can be segmented into four Subword Parallel single-precision Multiplier-And-Accumulators, which is shown in FIG. 1(b). Each Subword Parallel single-precision Multiplier-And-Accumulators includes four single-precision Multiplier-And-Accumulators, three left-shifters, and wallet tree adder (533). Those four single-precision Multiplier-And-Accumulators such as SM0 single-precision multiplier (520), SM1 single-precision multiplier (521), SM2 single-precision multiplier (522), and SM3 single-precision multiplier (523). Three left-shifters are SH0 left-shift $\frac{N}{2}$

[0123] bit

[0124] shifter (530), SH1 left-shift $\frac{N}{2}$

[0125] bit shifter (531), and left-shift-N-bit shifter (532).

[0126] The double-precision multiplication product is derived from the products pp0, pp1, pp2, pp3 by using the left-and-add method. The product pp0, shifted $\frac{N}{2}$

[0127] bit pp1, shifted $\frac{N}{2}$

[0128] bit pp2, and shifted-N-bit pp3 are summed to be the 2N-bit product of the double-precision multiplication.

[0129] If all the products pp0, pp1, pp2, and pp3 are configured with a group of complex accumulators, a group of single-precision complex-valued multiplier-and-accumulator is formed, as is shown in Figure IV. In this way, four parallel single-precision complex-valued multiplication-and-accumulations can be performed.

[0130] The differences of this new type of complex-valued multiplier-and-accumulator configuration from existing patents or known products are

[0131] 1.) the invention can be widely used in the complex-valued multiplication-accumulation in communication systems, as well as in the real-valued operation when processing general digital signals. On the other hand, the existing patents are for either complex number operation or for real number operation only.

[0132] 2.) the invention can perform both high- and low-precision multiplication-accumulation. Furthermore, the hardware can be fairly effectively used in the latter. Comparatively, the existing complex-valued multiplier or real-valued multiplier cannot sufficiently make use of all the hardware when performing subword parallel operations.

[0133] 3.) When performing a low-precision operation on the invention, Data alignment is not necessary, which has to be done in general subword Parallel operations. In parallel operations, each multiplication-accumulation operation brings three accumulated products for three successive iteration; they are for the present iteration, the previous iteration and the next iteration. So, in the parallel operation, operations for data alignment can be avoided.

[0134] Through proper multiplexing, this operation unit of invention can be applied in double (single)-precision complex (real)-valued multiplication-accumulations, thus being more flexible.

[0135] If four successive pairs of real-valued input into the four single-precision complex-valued multiplier-and-accumulator whose real numbers and imaginary numbers are as shown in Figure IV, through simple multiplexing and data movement, sixteen single-precision real-valued multiplication-addition can be performed in parallel in one cycle.

[0136] Each group of input into the multiplier-and-accumulator is related to each other, and through the operation results, we can verify that in each operation not only the present accumulated product but also the accumulated products for the previous iteration time and the next iteration time are computed. Therefore, before each multiplication-accumulation iteration, what we should do is only to move the accumulated value of the next output to the accumulators where the previous accumulated value is stored.

[0137] In this way, the invention can simply perform the sub-word parallel multiplication-and-accumulation without data-misaligned operation. This is due to the fact that we have already get the accumulated product in the data-aligned computation. This is why the extra processing for data alignment necessary in general Subword Parallel operation units can be omitted in this kind of complex-valued multiplier-and-accumulator.

N×N Double-Precision Complex-Valued Multiplier-And-Accumulator

[0138] The double-precision complex-valued multiplier is the main configuration, as shown in FIG. 1. AR and BR are real number registers 1 (3), respectively, and AI and BI are imaginary number register 2 (4), respectively. ACCR is real number accumulation register (201). ACC-AUX is auxiliary accumulation register (202). ACCI is imaginary number accumulation register (203).

[0139] In this architecture, there are four double-precision real number multipliers for calculating the products of AR real number (1) times BR real number (3), AI imaginary number (2) times BI imaginary number (4), AR real number (1) times BI imaginary number (3), as well as AI imaginary number (2) times BR real number (4). Of which, the products are accumulated in ACCR real number accumulation register (201), and ACCI Imaginary numbers accumulation register (203). At this time, the multiplexer MUX1 selects P2 product (103) and the basic complex accumulator is formed. ${Y(n)} = {\sum\limits_{k = 0}^{K - 1}\quad {{C(k)} \cdot {X\left( {n - k} \right)}}}$

N×N Double-Precision Real-Valued Multiplier-And-Accumulator

[0140] Double-precision real-valued complication-accumulation can also be operated by the N×N double-precision complex-valued multiplier-and-accumulator indicated in FIG. 1. Take the K-tap finite impulse response filter in Figure II as an example.

[0141] In the above equation, C (k) is the filter coefficient, X (k) is input signal and Y (n) is output signal. In each complex-valued multiplication-and-accumulation operation, two pars of continuous real-valued sampling C (k) C (k+1) and X (n−k) X (n−k−1) can be input, and in each cycle of multiplication-and-addition, only the operation with data aligned with even-numbered index value to even-numbered index value is necessary. When K=6 in Figure II, the previous third operation brings the output Y(n−2) accumulated product, while the next third operation brings output Y (n) accumulated product, so we can get the output Y in each K/2 times of operation, and in each operation, we get half of the accumulated product which is necessary for the previous output Y (n−1), as well as half of the accumulated product which is necessary for the next output Y (n+1). So, when performing double-precision real-valued operation, the multiplexer MUX1 in FIG. 1(a) is set at 0, and before each cycle of multiplication-addition, move the next output accumulated summation, e.g. ACCI (203) in FIG. 1(a), to the previous output accumulation register, e.g. ACC-AUX(202) in FIG. 1. So, in the iteration n, the output value of Y (n) (301) and Y (n−1) (302) can be obtained. For this reason, the unaligned data operation between even numbered index values and odd numbered index values can be omitted. Thus, averagely, in each time, four double-precision real-valued multiplication-accumulations can be performed without data alignment processing. $\frac{N}{2} \times \frac{N}{2}$

Single-Precision Complex-Valued Multiplier-And-Accumulator

[0142] subword parallel operation segmentation can be performed in the four double-precision real number multipliers in the double-precision complex-valued multiplier-and-accumulator configuration. In Figure III, two products among can be represented by AX and BX (X can be in the case when R or I represents real or imaginary number double-precision input). That two products among originally in N×N double-multiple precision multiplier (501, 502, 503, 504) shown on Figure I. .AXH multiplicand most significant bits (1701), AXL multiplicand least significant bits (1702), BXH multiplier most significant bits (1703), BXL multiplier least significant bits (1704) use $\frac{N}{2} \times {\frac{N}{2}.}$

[0143] SM0 single-precision multiplier (520)˜SM3 single-precision multiplier (523) in Figure II to figure out the four secondary number products, this is partial product 1 (1801), partial product 2 (1802), partial product 3 (1803) and partial product 4 (1804), by performing left-shift-addition, then N×N double-precision products(1805) can be obtained. The N×N double-precision real number products (1805) can be used in the complex-valued operation or in real-valued multiplication-addition, corresponding hardware configuration is shown in FIG. 1(b). The four groups of product such as pp0, pp1, pp2 and pp3 can be used in single-precision multiplication-addition.

[0144] As shown in Figure IV, with all the 16 single-precision multipliers A0˜A15 (701˜716), through the left-shift-addition of four secondary number products, N×N double-precision real number product is obtained. The purpose of this design is to get the accumulated products for both double-precision operation and single-precision complex-valued operations.

[0145] When performing single-precision complex-valued operations, redefine the most significant bits AXH (1701) and BXH (1703) originally in Figure III as single-precision real numbers AXR and BXR respectively; redefine the original least significant bits AXL (1702) and BXL (1704) as single-precision imaginary numbers AXI and BXI respectively. Reformed configuration is shown in Figure IV, through accumulation of products of real number and real number (AXR×BXR) and imaginary and imaginary (AXI×BXI), we can get the real values of single-precision complex number accumulation. Through accumulation of products of real number and imaginary number (AXR×BXI) and imaginary number and real number (AXI×BXR), we can get the imaginary values of single-precision complex-valued accumulation. So the four N×N double-precision complex-valued multipliers originally in FIG. 1(a), e.g. C0 double-multiple precision multiplier (500)˜C3 double-multiple precision multiplier (503), can reform the four parallel operating $\frac{N}{2} \times \frac{N}{2}$

[0146] single-precision complex-valued multiplier-and-accumulator, within each multiplier, there is a group of complex-valued accumulators acc0˜acc3 (901˜904).

[0147] Let us take the K-tap finite impulse response filter as an example. The operation program is the same as that of finite impulse response filter in the mode of N×N double-precision real number FIR operation (see Figure II), except that the double-precision C (n) now is a combination of single-precision real number CR (n) and imaginary number CI (n); double-precision X (n) is a combination of single-precision real number XR (n) and imaginary number XI (n). Similarly, every $\frac{K}{2}$

[0148] cycles of operation we can figure out the output Y, and half of the accumulated product necessary for the previous output Y (n−1) (1002), as well as half of the accumulated product necessary for the next output Y (n+1) are obtained in each operation. Before each multiplication-accumulation iteration, move the next output accumulation value acc3 (904) to the previous output accumulation register acc2 (903), as shown by the arrow (1201), (1202). In this way, after each multiplication-accumulation iteration, add acc0 (901) to acc1 (902). Thus, we get the present output Y (n) (1001), while acc2 (903) is the previous output Y (n−1) (1002). Similarly, the operation of unaligned data for even numbers to odd numbers can be omitted, so averagely in each time, four N×N single-precision complex-valued multiplication-accumulatons can be performed. $\frac{N}{2} \times \frac{N}{2}$

Single-Precision Real-Valued Multiplier-And-Accumulator

[0149] When apply this configuration to K-tap finite impulse response filter by performing the single-precision real number operation, the operation program can be illustrated in Figure V (K=4). In every input, there are four continuous single-precision filter coefficient C (n) and four continuous single-precision input samples X (n). In each operation, sixteen single-precision multiplier products are generated at the same time. Observing all the products of present time t=n (2202) and previous fourth time t=n−4 (2201), we can see that among the sixteen products in each operation, four products can be accumulated to the present output Y (n) (2301) that is indicated in the rectangle, and three products can be accumulated to the previous output Y (n−1) (2302) indicated in the rhombus, two products can be accumulated to the previous second output Y (n−2) (2303) indicated in the ellipse, one product can be accumulated to the previous third output Y (n−3) (2304) indicated in the trapezoid; on the other hand, in the previous fourth time t=n−4 (2201) operation, there are also three products which can be accumulated to its next output Y (n−3) (2304), two can be accumulated to the following second output Y (n−2) (2303), and one can be accumulated to the following third output Y (n−1) (2302). By this formula, complex-valued multiplier-and-accumulator can be reformed into $\frac{N}{2} \times \frac{N}{2}$

[0150] single-precision real-valued multiplication-and-accumulation through multiplexers, as shown in Figure VI. Before each multiplication-accumulation iteration, move the contents in the register acc12 (1413) that has accumulated the following output to the register acc11 (1412) that has accumulated the previous third output, as shown by the arrow (1603); move the contents in the register acc6 (1407) that has accumulated the following second output to the register acc4 (1405) that has accumulated the previous second output, as shown by the arrow (1601); move the contents in the register acc7 (1408) that has accumulated the following third output to the register acc5 (1406) that has accumulated the previous output, as shown by the arrow (1602). In this way, four outputs are generated after each multiplication-addition cycle: Y (n) (1501) comes from acc0 (1401) plus acc2 (1403); Y (n−1) (1502) comes from acc1 (1402) plus acc5 (1406); Y (n−2) (1503) is acc4 (1405); Y(n−3) (1504) is acc11 (1412). Because one cycle of multiplication-addition is performed every four points of time, non-quadruple alignment operation can be omitted, and sixteen single-precision real-valued multiplication-accumulation can be performed at the same time in one operation.

[0151] Subword parallel Complex-Valued Multiplier-And-Accumulator of the invention can be operated in four different modes. For a typical multiplication-addition as in K-tap finite impulse response filter, when it performs $\frac{N}{2} \times \frac{N}{2}$

[0152] single-precision real-valued multiplication-addition (see Figure VII), the number of cycles for multiplication-addition can be reduced from K for typical Multiplier-And-Accumulator to K/16.

[0153] This invention have a new type of configuration, fit for different data format (including complex-(real-)valued and double-(single-)precision) multiplication-accumulation, and the data alignment necessary for single-multiple precision operation. All connoisseurs can test and verify this imagination and its reasonability in different ways. Following patent scopes can prove my idea in different ways: 

What is claimed is:
 1. The double-precision Complex-Valued Multiplier-And-Accumulator whether including four double-precision Multiplier-And-Accumulators, such as C0 double-precision multiplier, C1 double-precision multiplier, C2 double-precision multiplier, and C3 double-precision multiplier respectively; three accumulators as M1 Accumulator, M2 Accumulator, and M3 Accumulator; and four Subword Parallel single-precision Multiplier-And-Accumulators.
 2. A double-precision Complex-Valued Multiplier-And-Accumulator according to claim 1, the four Subword Parallel single-precision Multiplier-And-Accumulators including four single-precision Multiplier-And-Accumulators, such as SM0 single-precision multiplier, SM1 single-precision multiplier, SM2 single-precision multiplier, and SM3 single-precision multiplier, three left-shifter, such as SH0 left-shift $\frac{N}{2}$

bit shifter, SH1 left-shift $\frac{N}{2}$

bit shifter, and left-shift-N-bit shifter; and WAN wallet tree adder as well.
 3. The double-precision complex-valued accumulator, which can be applied to different data formats (including complex (real) valued and double-(single-) recision) multiplication-addition; the above Multiplicator-And-Accumulator contains a complex-valued Multiplier-And-Accumulator, which includes four double-precision multipliers and two real number and imaginary number accumulator; when performing double-precision real-valued multiplication and addition, extra auxiliary register is added to calculate the output together with the original real number and imaginary number accumulator.
 4. A double-precision complex-valued accumulator according to claim 3, four double-precision multipliers are all segmented into four single-precision multipliers by means of Subword Parallel, and then get double-precision product in the way of left-shift-addition.
 5. A double-precision complex-valued accumulator according to claim 3, whether performing single-precision complex-valued multiplication-addition, the products of the four single-precision multipliers in each of the double-precision multipliers can be added to a group of complex-valued accumulator, to reform four parallel operating single-precision complex-valued accumulators.
 6. A double-precision complex-valued accumulator according to claim 3, whether performing single-precision real-valued multiplication-addition, the products of the sixteen single-precision multipliers in the four double-precision multipliers can reform sixteen parallel operating single-precision real-valued accumulators through multiplexers.
 7. The Multiplier-And-Accumulator fit for different data formats (including complex (real) number and double-(single-)multiple precision), its operations used in the double-precision Complex-Valued Multiplier-And-Accumulator includes a pair of double-precision complex number as four double-precision value input and four double-precision real-valued multipliers to perform complex-valued multiplication; this pair of double-precision complex number, products from real number times real number and imaginary number times imaginary number together accumulate into complex number accumulated real number summation, while products from real number times imaginary number and products from imaginary number times real number together accumulate into imaginary number summation accumulated from complex numbers.
 8. A Multiplier-And-Accumulator that is fit for different data formats (including complex (real) number and double-(single-)precision) according to claim 7, whether operations used in the double-precision real-valued multiplication-addition includes: two pairs of respectively continuous double-precision real number as four double-precision value input to the second complex number multiplier, and four double-precision real-valued multipliers to perform complex-valued multiplication; through proper multiplexing, two output values can be obtained in each cycle.
 9. A Multiplier-And-Accumulator that is fit for different data formats (including complex (real) number and double-(single-)precision) according to claim 7, whether the two pairs of double-precision real number correspond to the second complex number and perform multiplication, then we can get the present output accumulated product, the previous output accumulated product and the next output accumulated product; before each multiplication-addition cycle, move the following output accumulated product to the previous output accumulation register.
 10. A Multiplier-And-Accumulator that is fit for different data formats (including complex (real) number and double-(single-)precision) according to claim 7, whether two pairs of input signal perform multiplication-addition cycling operation, leaving data alignment processing omitted.
 11. A Multiplier-And-Accumulator that is fit for different data formats (including complex (real) number and double-(single-)precision) according to claim 7, whether the designs of the four double-multiple precision multiplier include: the two multipliers in each double-precision multiplier can be identified as most significant and least significant single precision values; if the two multipliers to perform multiplication in single-precision real-valued multiplication and then add all the four products together by means of left-shift-add, thus we get double-precision product.
 12. A Multiplier-And-Accumulator that is fit for different data formats (including complex (real) number and double-(single-)precision) according to claim 7, whether operations used in single-precision complex-valued multiplication-addition include: double-precision multiplier design modes, to set most (least) significant values as real (imaginary) numbers in single-precision complex numbers; the product from most-significant-bits times most-significant-bits and the product from least-significant-bits times least-significant-bits can be accumulated into accumulated real number part, and the product from most-significant-bits times least-significant-bits together with the product from least-significant-bits times most-significant-bits can be accumulated into accumulated imaginary number part.
 13. A Multiplier-And-Accumulator that is fit for different data formats (including complex (real) number and double-(single-)precision) according to claim 7, whether is respectively one pair of complex-valued accumulator in four groups of single-precision Complex-Valued Multiplier-And-Accumulator, they form four groups of parallel operating single-precision complex-valued Multiplier-And-Accumulator; two respectively continuous single-precision complex numbers as four double-precision values are input into the above mentioned four single-precision complex-valued accumulators.
 14. A Multiplier-And-Accumulator that is fit for different data formats (including complex (real) number and double-(single-)precision) according to claim 7, whether among four groups of single-precision complex-valued accumulator, two can figure out the present output accumulated value, one group is for the previous output accumulated value, one is for the next output accumulated value; through proper multiplexing, the present output accumulated value and the previous output accumulated value in one time; before each multiplication-addition cycle, move the next output accumulated product into the previous output accumulation register; two pairs of input signal to perform one cycle of multiplication-addition, leaving data alignment processing omitted.
 15. A Multiplier-And-Accumulator that is fit for different data formats (including complex (real) number and double-(single-)precision) according to claim 7, whether operations used in single-precision real-valued multiplication-addition include: four pairs of respectively continuous single-precision real numbers as four double-precision values are input to the above mentioned four single-precision complex-valued accumulators, we can figure out the present output accumulated product, the previous, the previous second, the previous third, the next, the following second, and the following third output accumulated products; through proper multiplexing, four groups of output values can be obtained in one time; before each multiplication-addition cycle, move the next output accumulated product to the previous third output accumulation register, move the following second output accumulated product to the previous second output accumulation register, move the following third output accumulated product to the previous output accumulation register; the four pairs of input signal perform one multiplication-addition cycling operation every four points of time, leaving alignment processing omitted. 